This invention relates, in general, to high-speed digital testing systems and, more specifically, to optical testing of very large scale integrated circuit chips and boards.
With the increasing speed and number of input and output channels, or bits, of modern logic devices, the testing of such logic devices becomes a time consuming problem. With the advent of very large scale and high-speed integrated circuits, new testing procedures and systems are needed to improve the production testing of these components.
Optimum testing usually involves the operation of the device being tested at the normal speed of operation. The results of these tests can give information on the occurrence of any errors, the location of any errors that occur, and/or the type of error, that is, whether the error was a logic high or low. While all three error types may be important during early design and prototype production of the devices, later production of a confirmed and proven design may only require that the testing procedure indicate if any errors occur in the operation of the device.
Testing such devices usually involves the application of many signals to the input terminals, or pins, of the logic device and checking the output pins of the device to determine if the logic level on each pin is the desired value, usually by comparing it with reference values. Although this can be done by normal digital electronics, conventional circuits are usually too slow for the high-speed devices currently being produced. Therefore, the paralleling of several conventional electronic digital circuits is necessary to test all the bits of the high-speed device in a resonable time. However, even the paralleling of similar circuits which operate simultaneously in time presents problems due to the inability to suitably combine the outputs of these circuits into a single detection capability.
Therefore, it is desirable, and it is an object of this invention, to provide an improved testing system for high-speed, large scale logic devices having a plurality of input and output terminals. The system provided functions very quickly and is easily paralleled to permit simultaneous detection of several output channels of the device.